Non-volatile memory is widely used nowadays in computers and electronic devices that have data storage capability. Because non-volatile memory can retain the stored information even when not powered, it is typically used for the task of secondary storage, or long-term persistent storage. There are several types of non-volatile memory. An electrically erasable programmable read-only memory (EEPROM) is a type of non-volatile memory that can be erased and programmed by exposing it to an electrical charge. Another type of non-volatile memory is a flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell structure that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include portable computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code, system data such as a basic input/output system (BIOS), and other firmware for a computer system can typically be stored in flash memory devices as well.
There are two common types of flash memory array architectures—the “NAND” and “NOR” architectures. NAND flash memory devices are typically used as mass data storage devices, and NOR flash memory devices are typically used as information storage devices for processing data at a high speed. Although each type of flash architecture has its advantages and disadvantages, NAND flash memory devices are widely in use especially in applications such as removable universal serial bus (USB) interface storage devices. This is partly because NAND flash architecture requires less chip area to implement a given capacity of flash memory compared with NOR flash architecture.
As part of the manufacturing process, the memory arrays of memory devices are tested to find and repair flawed sections of the array with redundant memory array sections, such as redundant rows and columns, that are available for such purpose. In some of the tests, data test patterns that are designed to locate specific array flaws (e.g. shorted or open bit lines and columns, stuck at “0” or “1” memory cells, etc.) are written, or programmed, to the memory array. Once the selected test pattern has been programmed into the array, it is read back and compared against the expected, e.g., original, pattern that is still resident in, or has been loaded into, an input/output (I/O) buffer of the memory device.
For example, for read self error detect (SED) testing of a NAND flash memory device, the data stored in each page, e.g., row, of memory cells of the memory array is read to a first I/O buffer, e.g., a data register, of the memory device and compared to the expected data that is loaded into a second I/O buffer, e.g., a cache register, of the flash memory device. More specifically, for read SED testing of the flash memory devices on a burn-in-board (BIB), a parallel read page command is given to all the memory devices on the BIB. After each read of each page is complete, the tester serially loads each device's cache register with the expected data, which is to be compared with the data read from the respective page.
Although the loading of the expected data into the cache register of a memory device undergoing the read SED test is in parallel with the loading of the data into the other memory devices that are also undergoing the test, the loading of the expected data into a cache register is done in a serial fashion—one byte at a time. Typically, the internal read time for data to be read from a page of the memory array to the data register is about 50 uS (microsecond). In contrast, for a 4K-byte cache register (corresponding to a 4K-byte-per-page memory array), the time for the expected data to be serially loaded into the cache register is typically equal to the write cycle time (30 nS) multiplied by the number of bytes in the cache register (4,314 bytes), or about 129 uS. As can be seen, the time for serially loading data into the cache register is a large portion of the total test time for a read SED test. In addition to the relatively large amount of time required to load the expected data, the use of I/O equipment is necessary to provide the desired background data into the memory devices. As such, resources such as I/O equipment and time for personnel to set up the equipment are unavoidable in order to run a read SED test. The large total test time and resource overhead are undesirable especially in view of time to market and costs.
Accordingly, there is a need and desire for a technique to enable a memory device having non-volatile memory, as well as a memory device having volatile memory, to load its memory array with desired background data to reduce total test time and costs associated with testing.